Design Verification Engineer

Responsibilities:

• Take technical ownership of assigned modules, guiding the team on implementation approaches and resolving technical roadblocks.
• Mentor team members to strengthen their technical skills and output, while tracking project status and flagging risks or escalations early.
• Ensure the assigned module follows required processes and contribute to technical reviews and discussions.

Requirements:

• Bachelor’s degree in Electronics, Electrical Engineering, or an equivalent field.
• At least 2 years of experience as a Design Verification Engineer or in an equivalent role, with solid understanding of the ASIC/SoC development lifecycle.
• Hands-on experience with OVM/UVM verification methodology using SystemVerilog.
• Experience building and maintaining full-chip test plans, developing and modifying testbenches and test cases, and running coding, execution, bug analysis, regressions, coverage analysis, and verification closure.
• Familiarity with common industry protocols and standards, such as PCIe Gen3/4/5, USB3, DDR4/5, Ethernet, CSI2, I3C, and AMBA.
• Experience with gate-level simulation and scripting.
• Track record of carrying at least one ASIC/SoC project through verification to tape-out.
• Good English skills required.

HOW TO APPLY: Please send your CV to the consultant in charge:

Ms. Huyen Hoang

E-mail: huyen.hoang@ev-search.com

All applications will be considered without regard to race, color, religion, sex (including pregnancy and gender identity), national origin, political affiliation, sexual orientation, marital status, disability, genetic information, age, membership in an employee organization, parental status, military service, or any other non-merit factor.