Physical Design Engineer

Responsibilities:

• Own the full RTL/Gate-level Netlist to GDSII implementation flow for individual blocks or the entire chip, including floor planning, power planning, clock tree synthesis, and signal integrity.
• Take ownership of physical implementation for assigned design partitions, delivering timing-clean blocks that meet sign-off criteria (DRC, LVS, IR drop) and are ready for tape-out.
• Drive timing closure through static timing analysis, and carry designs through physical verification and final sign-off.

Requirements:

• Bachelor’s or Master’s degree in Electronics, Electrical, or Computer Engineering, or an equivalent field.
• At least 2 years of hands-on Physical Design experience, with working knowledge of place-and-route tools (Cadence Innovus, Synopsys IC Compiler II/Fusion Compiler), timing and power tools (PrimeTime, Tempus, Voltus/PowerReplay), and physical verification tools (Calibre, Pegasus, or IC Validator).
• Familiarity with RTL/Netlist-to-GDSII flows, multi-Vt and multi-voltage design, low-power techniques (UPF/COPF), DFT-aware implementation, and advanced process nodes (28nm down to 3nm preferred).
• Comfortable scripting in Python, Perl, or Shell for flow automation.
• Strong analytical and debugging ability, with good cross-functional communication.

HOW TO APPLY: Please send your CV to the consultant in charge:

Ms. Huyen Hoang

E-mail: huyen.hoang@ev-search.com

All applications will be considered without regard to race, color, religion, sex (including pregnancy and gender identity), national origin, political affiliation, sexual orientation, marital status, disability, genetic information, age, membership in an employee organization, parental status, military service, or any other non-merit factor.